The present invention relates generally to a memory device, and more particularly, to a spin transfer torque magnetic random access memory (STT-MRAM) device having via landing pads in peripheral circuit thereof.
Spin transfer torque magnetic random access memory (STT-MRAM) is a new class of non-volatile memory, which can retain the stored information when powered off. A STT-MRAM device normally comprises an array of memory cells, each of which includes at least a magnetic memory element and a selection transistor coupled in series between appropriate electrodes. Upon application of an appropriate current to the magnetic memory element, the electrical resistance of the magnetic memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
The magnetic memory element typically includes at least a magnetic reference layer and a magnetic free layer with a non-magnetic tunnel junction layer interposed therebetween, thereby forming a magnetic tunneling junction (MTJ). The magnetic reference layer has a fixed magnetization direction and may be anti-ferromagnetically exchange coupled to a magnetic pinned layer, which has a fixed but opposite or anti-parallel magnetization direction. Upon the application of an appropriate current through the MTJ, the magnetization direction of the magnetic free layer can be switched between two directions: parallel and antiparallel with respect to the magnetization direction of the magnetic reference layer. The non-magnetic tunnel junction layer is normally made of an insulating material with a thickness ranging from a few to a few tens of angstroms. When the magnetization directions of the magnetic free and reference layers are substantially parallel, electrons polarized by the magnetic reference layer can tunnel through the insulating tunnel junction layer, thereby decreasing the electrical resistivity of the MTJ. Conversely, the electrical resistivity of the MTJ is high when the magnetization directions of the magnetic reference and free layers are substantially anti-parallel. Accordingly, the stored logic in the magnetic memory element can be switched by changing the magnetization direction of the magnetic free layer.
Based on the relative orientation between the magnetic reference and free layers and the magnetization directions thereof, a MTJ can be classified into one of two types: in-plane MTJ, the magnetization directions of which lie substantially within a plane parallel to the same layers, or perpendicular MTJ, the magnetization directions of which are substantially perpendicular to the plane.
A STT-MRAM device can be divided into a memory region including MTJ memory elements for storing information, and a peripheral circuit region including various types of peripheral circuit devices for detecting states in memory elements, controlling memory elements, and input/output operations. Fabrication of the MTJ memory elements are designed to be integrated into the back end wiring structure of back-end-of-line (BEOL) CMOS process following front-end-of-line (FEOL) CMOS process, in which selection and logic transistors are fabricated.
FIG. 1 is a cross sectional view of a conventional STT-MRAM device having a memory cell region 50 and a peripheral circuit region 52. The memory region 50 includes a plurality of MTJ memory elements 53 disposed on top of memory landing pads 56. Each of the plurality of the MTJ memory elements 53 includes a MTJ 54 and a top electrode 55 disposed thereon. The MTJ 54 comprises a magnetic reference layer 58 and a magnetic free layer 60 with a non-magnetic tunnel junction layer 62 interposed therebetween. The memory landing pads 56 are disposed on top of memory bottom contacts 64, which are coupled to selection transistors (not shown) formed in the FEOL process. The top electrode 55 disposed on top of the MTJ 54 is electrically connected to top metal wires (not shown) directly or through an optional via stud (not shown). The periphery circuit region 52 includes at least a periphery landing pad 56′ disposed on top of a periphery bottom contact 64′. A via 68 is disposed on top of the periphery landing pad 56′ and is coupled to a metal wire thereabove. Hence, the transistor (not shown) in the periphery circuit region 52 is connected to the metal wire above through a succession of the periphery bottom contact 64′, the periphery landing pad 56′, and the via 68.
According to the design rule for semiconductor manufacturing process, the minimum size of the landing pads 64 and 64′ in FIG. 1 is approximately 15 F2, where F denotes the minimum feature size that can be reliably manufactured for a technology node. Since a minimum clearance between adjacent landing pads is needed, the effective space or footprint required for each landing pad is increased to approximately 20 F2. Therefore, the cell size of a MTJ memory may easily exceeds 30 F2 when the placement of corresponding selection transistor is taken into account.
A possible approach to reducing the memory cell size is by removing the landing pads, as shown in FIG. 2. While this approach allows more closer packing of the memory cells in the memory region, the alignment error between the periphery bottom contact 64′ and the via 68 disposed thereon may reduce device yield, especially at small feature sizes.
Therefore, there is a need for a via landing pad in the peripheral circuit of a MRAM device that does not increase the memory cell size.